1. Field of the Invention
The present invention relates to an isolated switching power supply device that includes a main transformer arranged to transmit power from a primary side to a secondary side, and a power switch arranged to switch the current flowing to a primary coil of the main transformer from a DC input power supply, and outputs a desired direct voltage or direct current.
2. Description of the Related Art
The efficiency of a circuit can be increased by reducing the switching loss, and the switching loss can be reduced by zero voltage switching (ZVS). For example, an isolated switching power supply device including a voltage clamping circuit may be used as disclosed in Japanese Unexamined Patent Application Publication No. 2003-33016.
Such an isolated switching power supply device including a voltage clamping circuit is often used in the case where the output voltage is lower than the input voltage. FIG. 1 shows a known isolated switching power supply device. FIG. 2 shows waveform charts of some portions of the switching power supply device.
As shown in FIG. 1, the main transformer T1 includes a primary coil n1 and a secondary coil n2. On the primary side are disposed a voltage clamping circuit 2 defined by connecting a series circuit including a clamp capacitor C1 and a clamp switch Q2 to a primary coil n1 in series. The clamp switch Q2 is a p-type channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and has a parasitic diode in parallel. A switching control circuit 1 is a PWM (pulse width modulation) control IC that drives an active clamp converter. The switching control circuit 1 includes a power switch driving terminal outA, a clamp switch driving terminal outB, a feedback signal input terminal COMP and a ground terminal GND. The clamp switch driving terminal outB is connected to a level shift circuit including a diode D11 and a capacitor C10. The feedback signal input terminal COMP is connected to the light-receiving transistor of a photo coupler PC1.
The secondary side of the main transformer T1 includes synchronous rectifying devices Q3 and Q4, a choke coil L1, an output smoothing capacitor C3, resistors R2, R3 and R4, the ELD of the photo coupler PC1, and a shunt regulator SRG1.
The DC voltage applied between the terminals +Vin and −Vin of a DC input power supply is smoothed by an input smoothing capacitor C2, subsequently converted into an AC voltage by switching of a power switch Q1, and then transmitted from the primary coil n1 of the main transformer T1 to the secondary coil n2. The AC voltage is rectified by a rectifier circuit including a rectifying side switching device Q3 and a commutation side switching device Q4 and is then smoothed through a choke coil L1 and an output smoothing capacitor C3, thereby being converted into a DC voltage. An isolated switching power supply device having the above structure acts as an active clamp forward converter.
Driving signals are outputted from the terminals outA and outB of the switching control circuit 1. The output signal from the terminal outB is at the high (H) level over the period for which the output signal from the terminal outA is at the H level, and the H level period of the signal from the terminal outB starts earlier and ends later, thus being longer than that of the signal from the terminal outA. The output from the terminal outA is directly applied between the gate (G) and the source (S) of the n-type channel MOSFET or power switch Q1, and the output from the terminal outB is applied between the source (S) and the gate (G) of the p-type channel MOSFET or clamp switch Q2 through the level shift circuit including the capacitor C10 and the diode D11. Consequently, the power switch Q1 and the clamp switch Q2 are driven with complementary timing with dead time periods (t1 to t3 and t4 to t0 in FIG. 2) for which both switches are off. More specifically, PWM control is performed such that when the pulse width of the power switch Q1 is increased, the pulse width of the clamp switch Q2 is reduced, and when the pulse width of the power switch Q1 is reduced, the pulse width of the clamp switch Q2 is increased.
On the secondary side, the output voltage is divided by the resistors R3 and R4, and the divided voltages are input to the reference terminal of the shunt regulator SRG1. If the divided voltage increases beyond a specified value, the cathode current of the shunt regulator SRG1 is increased through the resistor R2 and the LED of the photo coupler PC1, and thus the current of the light-receiving transistor of the photo coupler PC1 is increased on the primary side. When the light-receiving transistor of the photo coupler PC1 is brought into conduction, the potential of the feedback signal input terminal COMP of the switching control circuit 1 is reduced to reduce the duty D of the power switch Q1. The output voltage Vout and the input voltage Vin of the forward converter, the turns ratio n2/n1 of the main transformer T1, and the duty D of the power switch Q1 have the following relationship:Vout=(n2/n1)·D·Vin
Hence, the output voltage is reduced by reducing the duty D. In contrast, if the divided voltage of the output voltage becomes lower than the specified value, the cathode current of the shunt regulator SRG1 running through the light-receiving transistor of the photo coupler PC1 is reduced to reduce the current flowing into the light-receiving transistor, and the potential of the feedback signal input terminal COMP of the switching control circuit 1 is increased to increase the duty D of the power switch Q1. The increase of the duty D increases the output voltage. Thus, the PWM control is performed so that the output voltage becomes constant.
As shown in FIG. 2, when the output of the terminal outA changes to the high (H) level from the low (L) level at time t0, the power switch Q1 is turned on and a current substantially proportional to the current of the choke coil L1 flows to the power switch Q1. When the power switch Q1 is turned off at time t1 and the voltage between the drain and the source of the power switch Q1 (Q1 D-S voltage) increases beyond the input voltage, LC resonance occurs between the excitation inductance of the transformer T1 and the parasitic capacitance present parallel to the D-S portion of the power switch Q1 (between times t1 and t2). If the D-S voltage of the power switch Q1 increases beyond the voltage between the ends of the clamp capacitor C1 at time t2, the parasitic diode of the clamp switch Q2 is brought into conduction and LC resonance occurs between the excitation inductance of the transformer T1 and the capacitance of the clamp capacitor C1. Since the capacitance of the clamp capacitor C1 is higher than the parasitic capacitance parallel to the D-S portion of the power switch Q1, the changes in the D-S voltage of the power switch Q1 become small and the waveform becomes such that the D-S voltage is clamped to substantially a constant value.
When the clamp switch Q2 is turned on at time t3 in the period for which the parasitic diode is in conduction, the LC resonance between the excitation inductance of the transformer T1 and the capacitance of the clamp capacitor C1 extends to reverse the direction of the exciting current. When the clamp switch Q2 is turned off at time t4 in the period for which an exciting current flows from the clamp capacitor C1 to the primary coil n1 of the transformer T1, the capacitance of the clamp capacitor C1 is removed from the circuit in which the LC resonance occurs, the resonance capacitance becomes the parasitic capacitance parallel to the D-S portion of the power switch Q1 again. Consequently, the resonance capacitance is reduced to reduce the D-S voltage of the power switch Q1 rapidly. Then, the power switch Q1 is turned on again at time t0 in the following cycle.
Surge voltage between both ends of the power switch Q1 is prevented by a clamping operation, and accordingly, a low-withstand-voltage transistor can be used as the power switch Q1. In addition, the electromagnetic energy of the transformer T1 absorbed by the clamp capacitor C1 can be regenerated by the LC resonance operation, and thus, highly efficient characteristics can be achieved.
In the switching power supply shown in FIG. 1, a direct current of about 10 V occurs between the ground terminal GND of the switching control circuit 1 and the source terminal or reference terminal of the clamp switch Q2. A clamp switch driving circuit can be composed of the level shift circuit including the capacitor C10 and the diode D11.
FIG. 3 shows another known isolated switching power supply device. FIG. 4 shows waveform charts of some portions of the switching power supply device.
The isolated switching power supply device shown in FIG. 3 is different from that shown in FIG. 1 in that the voltage clamping circuit 2 is disposed in a different position and a drive transformer T4 is used. Also, the clamp switch is not a p-type, but an n-type channel MOSFET. The other structure is substantially the same as that shown in FIG. 1. Driving signals outputted from the terminals outA and outB of the switching control circuit 1 come into the H level with complementary timing with dead time periods for which both signals are at the L level (time t1 to t3 and t4 to t0 in FIG. 4). Accordingly, the power switch Q1 and the clamp switch Q2 are driven with complementary timing with dead time periods. The operation of the voltage clamping circuit 2 shown in FIG. 3 is the same as the operation of the voltage clamping circuit 2 shown in FIG. 1. The potential of the source terminal of the clamp switch Q2 with respect to the ground terminal GND of the switching control circuit 1 is varied in an alternating manner by the switching operation of the power switch Q1. Accordingly, the output voltage from the clamp switch driving terminal outB is transmitted through the drive transformer T4, and thus a driving signal is applied between the gate and the source of the clamp switch Q2 through the level shift circuit including the diode D11 and the capacitor C10.
If a high input voltage is applied to a converter, it is required that the voltage clamping circuit 2, which is a series circuit of the clamp switch Q2 and the capacitor C1, be connected to the power switch Q1 in parallel, as shown in FIG. 1, so as to directly drive the clamp switch Q2 with an output signal from the switching control circuit 1. Accordingly, a p-type channel FET is inevitably used as the clamp switch Q2.
However, the p-type channel FET has a high on-resistance, and the product of the on-resistance and the input capacitance is about three times as high as that of an n-type channel MOSFET. Thus, the switching loss of the p-type channel FET is undesirably larger than that of the n-type channel FET. Therefore, isolated switching power supply devices including a p-type channel FET as the clamp switch Q2 are not suitable for application requiring relatively high power.
In order to use an n-type channel FET as the clamp switch, however, the voltage clamping circuit 2, which is a series circuit of the clamp switch Q2 and the clamp capacitor C1, is connected to the primary coil n1 of the main transformer T1 in parallel, as shown in FIG. 3. Consequently, the clamp switch Q2 cannot be directly driven by the output signal from the switching control circuit 1, and a drive transformer T4 is necessary.
On the other hand, in order to transmit square waves of switching frequency at a low loss, the drive transformer T4 requires a relatively high excitation inductance (for example, 100 μH or more). Accordingly, the number of turns of the primary coil and the secondary coil of the drive transformer T4 must be increased. This results in a high-cost and a large-size device.
If in order to reduce the surge voltage of the power switch Q1, a voltage clamping circuit is disposed on the secondary side of the main transformer T1 so that the voltage clamping circuit can be driven from the primary side through a drive transformer, it is required that the drive transformer have a withstand voltage (for example, 1500 V DC) satisfying safety standards. This undesirably results in a larger size and a higher cost.